Open AccessA Reconfigurable Hardware Architecture for Packet Processing
Author(s) -
DUAN Tong,
LAN Julong,
HU Yuxiang,
LIU Shiran
Publication year - 2018
Publication title -
chinese journal of electronics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.267
H-Index - 25
eISSN - 2075-5597
pISSN - 1022-4653
DOI - 10.1049/cje.2017.08.018
Subject(s) - computer science , architecture , computer architecture , network packet , packet processing , computer hardware , embedded system , parallel computing , computer network , art , visual arts
In this paper, we propose a reconfigurable packet processing hardware architecture for future switch, in which several protocol‐independent action units are introduced to remove the protocol dependence of conventional packet processors. With the proposed architecture, any specified header fields can be mapped into the right action unit, so that the processor can meet any packet processing demands. To reduce the hardware resource cost, the processor cost model and optimization algorithm are proposed. The NetFPGA‐based implementation shows a throughput of 94Gb/s with 64‐B packets. The programmability cost is approximately 1.5 times of conventional design, which consumes only 8% of the total FPGA resources.