Open AccessCache Power Optimization Based on Compare‐Based Adaptive Clock Gating and Its 65nm SoC Implementation
Author(s) -
Li Jie,
Wan Xing,
Wu Jianbing,
Shan Weiwei
Publication year - 2017
Publication title -
chinese journal of electronics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.267
H-Index - 25
eISSN - 2075-5597
pISSN - 1022-4653
DOI - 10.1049/cje.2016.06.029
Subject(s) - cache , clock gating , computer science , idle , embedded system , benchmark (surveying) , power gating , overhead (engineering) , cpu cache , cache pollution , microprocessor , smart cache , power optimization , power (physics) , reduction (mathematics) , parallel computing , power consumption , cache coloring , cache algorithms , transistor , voltage , clock skew , clock signal , engineering , electrical engineering , operating system , telecommunications , quantum mechanics , jitter , physics , mathematics , geometry , geodesy , geography
In most embedded microprocessor based System on chips (SoCs), cache has become a major source of power consumption due to its increasing size and high access rate. Power optimization of cache based on Compare‐based adaptive clock gating (CACG) is proposed to reduce the power waste due to cache idle. By detecting the cache's working state, the CACG can automatically turn off its clock when it is in idle state, saving a large percentage of dynamic power. Measurements of a real SoC chip fabricated under TSMC 65nm CMOS process show that an average of 30.3% power reduction is gained in Dhrystone test benchmark at a cost of negligible area overhead and no virtually performance loss.