On‐Chip Generating FPGA Test Configuration Bitstreams to Reduce Manufacturing Test Time | Zendy

Wang Fei | Zendy; Wang Da | Zendy; Yang Haigang | Zendy; Xie Xianghui | Zendy; Fan Dongrui | Zendy

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On‐Chip Generating FPGA Test Configuration Bitstreams to Reduce Manufacturing Test Time

Author(s) -

Wang Fei,

Wang Da,

Yang Haigang,

Xie Xianghui,

Fan Dongrui

Publication year - 2016

Publication title -

chinese journal of electronics

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.267

H-Index - 25

eISSN - 2075-5597

pISSN - 1022-4653

DOI - 10.1049/cje.2016.01.010

Subject(s) - field programmable gate array , computer science , chip , embedded system , test (biology) , parallel computing , computer hardware , geology , telecommunications , paleontology

Statistics shows that over 95% of FPGA manufacturing test time is spent on loading test configuration bitstreams. Reducing the test time that spent on loading test configuration bitstreams could significantly reduce FPGA test time. A new approach which can significantly reduce the FPGA test time is presented. Experimental results show that the proposed technique can at least reduce the configuration loading time by 96%, while getting 100% test coverage with less than 1.2% hardware overhead.

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