Open AccessEfficiently Exploring FPGA Design Space Based on Semi‐Supervised Learning
Author(s) -
Yang Liqun,
Yang Haigang,
Li Wei,
Li Zhihua
Publication year - 2016
Publication title -
chinese journal of electronics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.267
H-Index - 25
eISSN - 2075-5597
pISSN - 1022-4653
DOI - 10.1049/cje.2016.01.009
Subject(s) - field programmable gate array , computer science , architecture , space (punctuation) , tree (set theory) , design space exploration , gate array , computer engineering , artificial intelligence , computer architecture , embedded system , mathematics , operating system , art , mathematical analysis , visual arts
Design space exploration (DSE) is an important step before the physical level design of Field programmable gate arrays (FPGA). An optimum architecture is usually selected from the whole space. As the architecture parameters increase, the huge time cost to explore an exponentially increasing space makes this method unrealistic. We propose a novel predictive modeling approach called ECOMT to estimate the area and delay of a circuit which is mapped onto an FPGA with certain architecture. Semi‐supervised model tree is adopted to model the performance with respect to architecture parameters. Combined with nonlinear programming, the area and delay model obtained can be used to guide the DSE. Experimental results show that the model trained through ECOMT has Mean relative error (MRE) below 5% compared to VTR. Meanwhile the time used to attain the model is less than 3 minutes, which reduces the time of DSE considerably.