Open AccessAutomatic diagnosis of single fault in interconnect testing of SRAM‐based FPGA
Author(s) -
Nirmalraj T.,
Radhakrishnan S.,
Pandiyan S.K.
Publication year - 2021
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
eISSN - 1751-861X
pISSN - 1751-8601
DOI - 10.1049/cdt2.12028
Subject(s) - field programmable gate array , benchmark (surveying) , interconnection , fault coverage , static random access memory , fault (geology) , computer science , fault detection and isolation , parallel computing , embedded system , electronic circuit , engineering , algorithm , computer hardware , artificial intelligence , electrical engineering , seismology , geology , computer network , geodesy , actuator , geography
Fault detection and diagnosis of a Field‐Programmable Gate Array (FPGA) in a short period is vital particularly in reducing the dead time of critical applications that are running on FPGAs. Thus, this paper proposes a new technique that is able to uniquely identify any single stuck‐at fault's location along with the type of fault. Also, the presented technique is able to locate any single pair‐wise bridging fault and distinguish between the two types of common faults. The presented technique uses the Walsh Code method to significantly reduce the number of test configurations when compared with previous methods. Extensive testing of the proposed method is carried out on a series of ISCAS’89 benchmark circuits being implemented in different FPGA families. From the simulation results, the maximum number of configurations needed for interconnect fault detection and diagnosis islog 2 ( n ( n − 1 ) 2 ) + 3 where n is the number of nets under test. It is noted that the proposed method is able to reduce the total number of test configurations bylog 2 ( n + 2 )when compared with previously published methods available in the literature.