Open AccessLow‐space bit‐serial systolic array architecture for interleaved multiplication over GF(2 m )
Author(s) -
Ibrahim Atef
Publication year - 2021
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
eISSN - 1751-861X
pISSN - 1751-8601
DOI - 10.1049/cdt2.12026
Subject(s) - multiplier (economics) , very large scale integration , application specific integrated circuit , systolic array , computer science , arithmetic , gf(2) , cryptography , multiplication (music) , binary number , parallel computing , computer hardware , finite field , embedded system , mathematics , algorithm , discrete mathematics , combinatorics , economics , macroeconomics
Abstract This article offers a new bit‐serial systolic array architecture to implement the interleaved multiplication algorithm in the binary‐extended field. The exhibited multiplier structure is more proper for VLSI implementation as it has regular cell structures as well as local communication wires between the cells. The ASIC implementation results of the suggested bit‐serial multiplier structure and the existing competitive bit‐serial multiplier structures previously described in the literature indicate that the recommended design achieves a notable reduction in area and significant improvement of area‐time complexities by at least 28.4% and 35.7%, respectively. Therefore, it is more proper for cryptographic applications forcing more restrictions on the space.