Open AccessFPGA‐based implementation of floating point processing element for the design of efficient FIR filters
Author(s) -
John Tintu Mary,
Chacko Shanty
Publication year - 2021
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
eISSN - 1751-861X
pISSN - 1751-8601
DOI - 10.1049/cdt2.12010
Subject(s) - very large scale integration , finite impulse response , field programmable gate array , computer science , floating point , filter (signal processing) , digital filter , computer hardware , electronic engineering , embedded system , algorithm , engineering , computer vision
Numerous applications based on very large scale intergration (VLSI) architecture suffer from large size components that lead to an error in the design of the filter during the stages of floating point arithmetic. Hence, it is necessary to change the architectural model that increases the design complexity and the time delay effect. The issue encountered in the VLSI architectures for finite impulse response (FIR) filter is the increased number of components, especially delay elements. For the VLSI architecture reconfigured with reduced register usage, this article provides the floating point processing element (FPPE) implementation with Cross‐Folded Shifting. The proposed FIR filter system reduces the number of components in the circuit which increases the complexity and high delay rate in the logical operation. The system has a comparatively reduced delay rate and power consumption. Hence, an efficient fast architecture based on the FPPE method is developed in this paper.