Open AccessBinary decision diagram‐based synthesis technique for improved mapping of Boolean functions inside memristive crossbar‐slices
Author(s) -
Chakraborty Anindita,
Maurya Vivek,
Prasad Sneha,
Gupta Suryansh,
Chakraborty Rajat Subhra,
Rahaman Hafizur
Publication year - 2021
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
eISSN - 1751-861X
pISSN - 1751-8601
DOI - 10.1049/cdt2.12007
Subject(s) - crossbar switch , computer science , node (physics) , logic synthesis , boolean function , memristor , boolean circuit , logic gate , logic family , pass transistor logic , binary decision diagram , electronic circuit , and inverter graph , algorithm , theoretical computer science , parallel computing , topology (electrical circuits) , digital electronics , electronic engineering , engineering , electrical engineering , telecommunications , structural engineering
Memristors are two‐terminal nano‐electronic devices that make it possible to design non‐volatile memory and logic circuits with high integration density. The logic operations of memristor‐based circuits are performed by applying suitable voltages across them. Researchers have been widely experimenting with this device to efficiently implement particular logic functions. However, recently, a synthesis methodology for arbitrary logic functions has been reported, where an input Boolean function is first represented as a Binary Decision Diagram (BDD), followed by the mapping of the BDD‐nodes (netlists of 2‐input NOR and NOT gates) inside a cluster of sliced crossbar‐arrays. The authors propose to map the BDD‐nodes for any input Boolean function to the crossbar‐slices using an improved technique, where each BDD‐node is mapped more efficiently, and the node‐logic is implemented following the Memristor Aided loGIC (MAGIC) design style. Our proposed mapping‐based realization of a BDD‐node has superior performance and energy‐efficiency than the existing IMPLY and MAGIC‐based BDD‐node designs techniques, provided all three node‐designs are implemented inside the similar‐sized crossbars. Comparative‐study of the synthesis results showed that the memristive‐circuits generated using our proposed technique are 26.95% faster, and need 42.32% lesser memristors (on average) than their peers, implemented using the existing approach of slicing crossbar‐architecture.