Open AccessAn efficient loop tiling framework for convolutional neural network inference accelerators
Author(s) -
Huang Hongmin,
Hu Xianghong,
Li Xueming,
Xiong Xiaoming
Publication year - 2022
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/cds2.12091
Subject(s) - convolutional neural network , computer science , field programmable gate array , verilog , inference , feature (linguistics) , computer engineering , gate array , field (mathematics) , computer hardware , deep learning , artificial intelligence , parallel computing , mathematics , linguistics , philosophy , pure mathematics
Abstract Convolutional neural networks (CNNs) have been widely applied in the field of computer vision due to their inherent advantages in image feature extraction. However, it is difficult to implement CNNs directly on embedded platforms owing to excessive calculations of CNNs. Field Programmable Gate Arrays have been popular in CNN accelerators because of their configurability and high energy efficiency. Given the highly parallel workloads of the CNN, a CNN accelerator with a 14 × 16 processing element array is designed in this study to accelerate the CNN inference. Besides, a loop tiling strategy for convolutional layers is proposed to efficiently transmit feature maps. Additionally, the roofline model is employed to explore the best tiling parameters for optimal performance. Finally, the accelerator written in Verilog‐HDL language is implemented on the Xilinx Zynq‐7045 evaluation platform. At an operating frequency of 200 MHz, the proposed accelerator can achieve a performance of 57.24 giga operations per second on You Only Look Once v2‐tiny and 78.39 GOPS on Visual Geometry Group‐16. The accelerator only consumes 224 DSPs, demonstrating a better performance compared with the previous works.