Open AccessA low power and soft error resilience guard‐gated Quartro‐based flip‐flop in 45 nm CMOS technology
Author(s) -
Kumar Sabavat Satheesh,
Sundaram Kumaravel,
Padmanaban Sanjeevikumar,
HolmNielsen Jens Bo,
Blaabjerg Frede
Publication year - 2021
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/cds2.12052
Subject(s) - soft error , upset , cmos , flip flop , inverter , flops , computer science , redundancy (engineering) , single event upset , electronic engineering , electrical engineering , computer hardware , engineering , voltage , parallel computing , static random access memory , mechanical engineering , operating system
Conventional flip‐flops are more vulnerable to particle strikes in a radiation environment. To overcome this disadvantage, in the literature, many radiation‐hardened flip‐flops (FFs) based on techniques like triple modular redundancy, dual interlocked cell, Quatro and guard‐gated Quatro cell, and so on, are discussed. The flip‐flop realized using radiation hardened by design Quatro cell is named as the improved version of Quatro flip‐flop (IVQFF). Single event upset (SEU) at inverter stages of master/slave and at output are the two drawbacks of IVQFF. This study proposes a guard‐gated Quatro FF (GQFF) using guard‐gated Quatro cell and Muller C‐element. To overcome the SEU at inverter stages of IVQFF, in GQFF, the inverter stages are realized in a parallel fashion. A dual‐input Muller C‐element is connected to the GQFF output stage to mask the SEU and thus maintain the correct output. The proposed GQFF tolerates both single node upset (SNU) and double node upset (DNU). It also achieves low power. To prove the efficacy, GQFF and the existing FFs are implemented in 45 nm Complementary Metal Oxide Semiconductor (CMOS) technology. From the simulation results, it may be noted that the GQFF is 100% immune to SNUs and 50% immune to DNUs.