Open AccessEfficient FPGA based architecture for high‐order FIR filtering using simultaneous DSP and LUT reduced utilization
Author(s) -
Maamoun Mountassar,
Hassani Adnane,
Dahmani Samir,
Ait Saadi Hocine,
Zerari Ghania,
Chabini Noureddine,
Beguenane Rachid
Publication year - 2021
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/cds2.12043
Subject(s) - lookup table , field programmable gate array , finite impulse response , multiplexer , computer science , digital signal processing , computer hardware , parallel computing , filter (signal processing) , digital filter , multiplier (economics) , embedded system , multiplexing , algorithm , telecommunications , economics , computer vision , macroeconomics , programming language
This paper proposes an efficient high‐order finite impulse response (FIR) filter structure for field programmable gate array (FPGA)‐based applications with simultaneous digital signal processing (DSP) and look‐up‐table (LUT) reduced utilization. The real‐time updating of the filter coefficients is also put into perspective. In order to perform these objectives, both the speed and the structure of FPGA are efficiently exploited. The gap between the required input sampling frequency and the FPGA allowed maximum frequency is managed to achieve additional computing sequences. Furthermore, the special structures of the FPGA Look‐up‐table Shift‐Register (LUT‐SR) and their internal connections are fully employed for pipelining and selecting the input samples. The FPGA Block RAMs (BRAMs) are employed for handling the reconfigurable filter coefficients, and the FPGA DSP slices are associated for computing the output data of the BRAMs and the multiplexers. To synchronize the BRAM unit addressing with the LUT multiplexer selection, a single unit is used for simultaneous control. The obtained results show that the proposed reconfigurable 16‐tap FIR filter offers reductions of 79.3% and 74.4% of slice utilization over the hybrid variable size partitioning (VP‐Hybrid) based structure and the Radix‐2 r based structure, respectively when implemented on a Xilinx Spartan‐6 XC6SLX45 FPGA. Moreover, an improvement of efficiency is achieved compared to all reputed FPGA‐based architectures.