Fabrication of Graphoepitaxial Gate-All-Around Si Circuitry Patterned Nanowire Arrays Using Block Copolymer Assisted Hard Mask Approach

We demonstrate the fabrication of sub-20 nm gate-all-around silicon (Si) nanowire field effect transistor structures using self-assembly. To create nanopatterned Si feature arrays, a block-copolymer-assisted hard mask approach was utilized using a topographically patterned substrate with well-defined Si 3 N 4 features for graphoepitaxially alignment of the self-assembled patterns. Microphase-separated long-range ordered polystyrene- b -poly(ethylene oxide) (PS- b -PEO) block-copolymer-derived dot and line nanopatterns were achieved by a thermo-solvent approach within the substrate topographically defined channels of various widths and lengths. Solvent annealing parameters (temperature, annealing time, etc .) were varied to achieve the desired patterns. The BCP structures were modified by anhydrous ethanol to facilitate insertion of iron oxide features within the graphoepitaxial trenches that maintained the parent BCP arrangements. Vertical and horizontal ordered Si nanowire structures within trenches were fabricated using the iron oxide features as hard masks in an inductively coupled plasma (ICP) etch process. Cross-sectional micrographs depict wires of persistent width and flat sidewalls indicating the effectiveness of the mask. The aspect ratios could be varied by varying etch times. The sharp boundaries between the transistor components was also examined through the elemental mapping.