Power Dissipation of WSe2 Field-Effect Transistors Probed by Low-Frequency Raman Thermometry
Author(s) -
Amirhossein Behranginia,
Zahra Hemmat,
Arnab K. Majee,
Cameron J. Foss,
Poya Yasaei,
Zlatan Akšamija,
Amin SalehiKhojin
Publication year - 2018
Publication title -
acs applied materials and interfaces
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 2.535
H-Index - 228
eISSN - 1944-8252
pISSN - 1944-8244
DOI - 10.1021/acsami.8b04724
Subject(s) - materials science , dissipation , raman spectroscopy , transistor , field effect transistor , thermal management of electronic devices and systems , power (physics) , field (mathematics) , optoelectronics , nanotechnology , electrical engineering , optics , mechanical engineering , voltage , physics , quantum mechanics , mathematics , pure mathematics , thermodynamics , engineering
The ongoing shrinkage in the size of two-dimensional (2D) electronic circuitry results in high power densities during device operation, which could cause a significant temperature rise within 2D channels. One challenge in Raman thermometry of 2D materials is that the commonly used high-frequency modes do not precisely represent the temperature rise in some 2D materials because of peak broadening and intensity weakening at elevated temperatures. In this work, we show that a low-frequency E 2g 2 shear mode can be used to accurately extract temperature and measure thermal boundary conductance (TBC) in back-gated tungsten diselenide (WSe 2 ) field-effect transistors, whereas the high-frequency peaks (E 2g 1 and A 1g ) fail to provide reliable thermal information. Our calculations indicate that the broadening of high-frequency Raman-active modes is primarily driven by anharmonic decay into pairs of longitudinal acoustic phonons, resulting in a weak coupling with out-of-plane flexural acoustic phonons that are responsible for the heat transfer to the substrate. We found that the TBC at the interface of WSe 2 and Si/SiO 2 substrate is ∼16 MW/m 2 K, depends on the number of WSe 2 layers, and peaks for 3-4 layer stacks. Furthermore, the TBC to the substrate is the highest from the layers closest to it, with each additional layer adding thermal resistance. We conclude that the location where heat dissipated in a multilayer stack is as important to device reliability as the total TBC.
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