Research on Verification and Implementation of RTL-based VHDL Simulator | Zendy

Ming Leng | Zendy; Lingyu Sun | Zendy

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Research on Verification and Implementation of RTL-based VHDL Simulator

Author(s) -

Ming Leng,

Lingyu Sun

Publication year - 2012

Publication title -

energy procedia

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.474

H-Index - 81

ISSN - 1876-6102

DOI - 10.1016/j.egypro.2012.01.084

Subject(s) - vhdl , computer science , central processing unit , register transfer level , computer architecture simulator , set (abstract data type) , logic simulation , computer architecture , instruction set , hardware description language , logic synthesis , embedded system , parallel computing , operating system , programming language , logic gate , field programmable gate array , algorithm

VHDL simulator based on Register Transfer Level (RTL) is implemented and verified, named RVS. Firstly, we give the implementation of RVS. Secondly, we design the micro program SAP-CPU and logic SAP-CPU based on VHDL language, which includes the format of control instruction, instruction set, addressing method, test program and the architecture of logic SAP-CPU and micro program SAP-CPU. Finally, the experiment and analysis show that the simulator of RVS perform well and produce encouraging solutions correctly on two SAP-CPU designs controlled by combinational logic and micro-program

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