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Via Minimization with Pin Preassignments and Layer Preference
Author(s) -
Grötschel M.,
Jönger M.,
Reinelt G.
Publication year - 1989
Publication title -
zamm ‐ journal of applied mathematics and mechanics / zeitschrift für angewandte mathematik und mechanik
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.449
H-Index - 51
eISSN - 1521-4001
pISSN - 0044-2267
DOI - 10.1002/zamm.19890691107
Subject(s) - minification , very large scale integration , printed circuit board , layer (electronics) , preference , electronic circuit , computer science , integrated circuit , algorithm , mathematics , mathematical optimization , embedded system , electrical engineering , engineering , materials science , statistics , nanotechnology , operating system
The problem of minimizing the number of vias subject to pin preassignments and layer preferences comes up in VLSI respectively printed circuit board design. It can be formulated as a max‐cut problem. In this paper, we discuss the application of approximative algorithms for the max‐cut problem to minimize the number of vias of (real‐world) electronic circuits.