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Analysis and elimination of circulating current caused by dead time for a grid‐connected inverter parallel system
Author(s) -
Song Chunwei,
Zeng Zheng
Publication year - 2018
Publication title -
ieej transactions on electrical and electronic engineering
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.254
H-Index - 30
eISSN - 1931-4981
pISSN - 1931-4973
DOI - 10.1002/tee.22717
Subject(s) - pulse width modulation , dead time , inverter , control theory (sociology) , current (fluid) , grid , voltage , modulation (music) , generator (circuit theory) , computer science , electronic engineering , sampling (signal processing) , engineering , electrical engineering , power (physics) , physics , mathematics , filter (signal processing) , acoustics , geometry , control (management) , quantum mechanics , artificial intelligence
In this paper, the circulating current caused by dead time is discussed for a grid‐connected inverter parallel system (GIPS) with common/isolated DC link. When the dead times for parallel units are different, the instantaneous output pulse width modulation (PWM) voltages cannot be synchronous, generating a circulating current. According to the operating modes, the trend of variation of the circulating current is revealed in one sampling period. In order to eliminate the circulating current caused by the dead time, dead‐time elimination sinusoidal pulse‐width modulation (SPWM) is applied to GIPS. The dead‐time elimination PWM generator is integrated into the field‐programmable gate array (FPGA). Experimental results are presented to demonstrate the validity and features of the proposed dead‐time elimination SPWM. © 2018 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.