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Bio‐inspired network on chip having both guaranteed throughput and best effort services using fault‐tolerant algorithm
Author(s) -
Sethi Muhammad Athar Javed,
Hussin Fawnizu Azmadi,
Hamid Nor Hisham
Publication year - 2018
Publication title -
ieej transactions on electrical and electronic engineering
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.254
H-Index - 30
eISSN - 1931-4981
pISSN - 1931-4973
DOI - 10.1002/tee.22678
Subject(s) - router , fault tolerance , computer science , quality of service , network on a chip , network packet , computer network , embedded system , distributed computing
Network‐on‐chip (NoC) is a communication framework for multiple cores connected together in a system‐on‐chip (SoC). Different NoC architectures have provided quality of service (QoS) parameters of best effort (BE) and guaranteed throughput (GT). GT services are provided by having a dedicated connection using circuit switching or connection‐oriented mechanism of packet switching. GT traffic is usually preferred for real‐time traffic such as video processing and multimedia applications. BE services are provided using packet switching. Cache updates is an example of BE noncritical traffic. In this paper, we implement a novel biologically inspired fault‐tolerant algorithm that provides both GT and BE QoS. In order to provide fault tolerance, the router architectures is also updated. The bio‐inspired, fault‐tolerant techniques are a novel way to provide fault tolerance in NoC. Faults in the NoC arise as the size of the devices are shrinking on the NoC, which include the router, links, and processing elements (PEs), to accommodate the complex communication requirements of applications. The proposed NoC's fault‐tolerant methods (synaptogenesis and sprouting) are adapted from the biological brain's robust fault‐tolerant mechanisms. From the experimental results, the throughput and bandwidth utilization are dropped by 3.55 and 4.87%, respectively, during the recovery from faults. The interflit arrival time and packet network latency are increased by only 7.03 and 22.60%, respectively, during the recovery from faults. The algorithm also performs as efficiently as the traditional fault‐tolerant techniques. © 2018 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.