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An efficient method for reconfiguring power‐efficient VLSI array with maximum satisfiability
Author(s) -
Qian Junyan,
Chen Cong,
Zhao Lingzhong,
Guo Yunchuan
Publication year - 2018
Publication title -
ieej transactions on electrical and electronic engineering
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.254
H-Index - 30
eISSN - 1931-4981
pISSN - 1931-4973
DOI - 10.1002/tee.22628
Subject(s) - very large scale integration , maximum satisfiability problem , satisfiability , solver , control reconfiguration , computer science , boolean satisfiability problem , parallel computing , power (physics) , algorithm , embedded system , boolean function , physics , quantum mechanics , programming language
Techniques to determine subarrays when processing elements (PEs) of very large scale integration (VLSI) arrays become faulty have been investigated extensively. In this paper, we propose a maximum satisfiability (MaxSAT)‐based method for the reconfiguration of a two‐dimensional degradable VLSI array with faulty PEs. A MaxSAT model is developed such that the target array can be constructed utilizing the efficient MaxSAT solver. Using the proposed method, we are able to find a maximum logical array with the least number of long interconnects and minimizing the number of the long interconnects that will lead to less rerouting costs. Experimental results show that the proposed method is able to reduce most redundant interconnects for the host array compared to earlier works. © 2018 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.