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Efficient abstraction algorithms for accelerating reconfiguration of VLSI arrays
Author(s) -
Qian Junyan,
Bai Zhangshun,
Zhou Zhide,
Zhao Lingzhong,
Chang Liang
Publication year - 2017
Publication title -
ieej transactions on electrical and electronic engineering
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.254
H-Index - 30
eISSN - 1931-4981
pISSN - 1931-4973
DOI - 10.1002/tee.22463
Subject(s) - control reconfiguration , very large scale integration , abstraction , computer science , operability , fault (geology) , row , fault tolerance , reliability (semiconductor) , algorithm , parallel computing , embedded system , distributed computing , power (physics) , philosophy , epistemology , database , physics , software engineering , quantum mechanics , seismology , geology
Employment of fault‐tolerant techniques is necessary for the operability and reliability of very large scale integration (VLSI) arrays. Moreover, fault tolerance must be obtained at high speed on real‐time embedded systems. In this paper, a novel abstract model, based on the abstraction technique, is proposed to accelerate the reconfiguration of degradable VLSI arrays with low fault density. Given an m × n physical array with faults, the proposed technique extracts some physical rows including faulty elements to construct an abstraction array, ignoring the physical rows without faults, such that the size of original physical array can be significantly reduced to speed up the reconfiguration of VLSI array. In addition, we conclusively demonstrate the preservation of properties between the abstract array and the physical array to guarantee that the proposed technique is correct. Experimental results show that for a 128 × 128 physical array with 0.1% faults, a 15 × 128 abstract array can be constructed and the compression is more than 88.20%. This abstraction technique is bound into a reconfiguration algorithm cited in this paper. Simulation results show that the running time can be improved by more than 66.79% for a 128 × 128 physical array with 0.1% faults. © 2017 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.