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Implementation and evaluation of an FPGA‐based network data anonymizer
Author(s) -
Nakamura Yuichi,
Sawaguchi Sota,
Nishi Hiroaki
Publication year - 2017
Publication title -
ieej transactions on electrical and electronic engineering
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.254
H-Index - 30
eISSN - 1931-4981
pISSN - 1931-4973
DOI - 10.1002/tee.22426
Subject(s) - computer science , the internet , anonymity , network packet , service provider , key (lock) , field (mathematics) , traverse , service (business) , computer network , computer security , world wide web , economy , mathematics , geodesy , geography , pure mathematics , economics
Privacy concern is a key element in recent Internet development, as more data transfers are acquired and analyzed while packets traverse the network. Data analysis can provide many benefits to internet service providers and users, such as recommendation services based on user activity on the Internet. While these services make use of the vast amounts of content and statistical data that can be acquired from network transactions, service providers face the challenge of ensuring that their services do not cause any privacy infringements. To cope with this problem, anonymization methods such as anonymity and l ‐diversity are commonly utilized to generalize datasets and eliminate private information. However, performing anonymization on a vast amount of data acquired from a network imposes high calculation costs. In this paper, we focus on proposing and implementing a field‐programmable gate array (FPGA)‐based data anonymizer to accelerate the anonymization of data that are used for internet services. A RAM‐based anonymizer is proposed and tested using real‐life internet traffic to evaluate how it performs under network applications. © 2017 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.