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A design guideline of parasitic inductance for preventing oscillatory false triggering of fast switching GaN‐FET
Author(s) -
Umetani Kazuhiro,
Yagyu Keisuke,
Hiraki Eiji
Publication year - 2016
Publication title -
ieej transactions on electrical and electronic engineering
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.254
H-Index - 30
eISSN - 1931-4981
pISSN - 1931-4973
DOI - 10.1002/tee.22339
Subject(s) - parasitic element , inductance , decoupling (probability) , capacitance , transistor , parasitic capacitance , oscillation (cell signaling) , equivalent circuit , electronic engineering , electrical engineering , computer science , materials science , optoelectronics , voltage , engineering , physics , electrode , chemistry , biochemistry , quantum mechanics , control engineering
Gallium nitride field‐effect transistors (GaN‐FETs) are attractive devices because of its low on‐state resistance and fast switching capability. However, they can suffer from false triggering caused by fast switching. Particularly, a disastrous oscillation of repetitive false triggering can occur after a turn‐off, which may deteriorate the reliability of power converters. To address this issue, we give a design guideline to prevent this phenomenon. We analyze a simple circuit model to derive the condition of occurrence of this phenomenon, which is then verified experimentally. Results show that the parasitic inductance of the gating circuit, L g , and that of the decoupling circuit, L d , should be designed so that the LC resonance frequency of L g and the gate–source capacitance of the GaN‐FET does not coincide with that of L d and the drain–source capacitance, respectively. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.