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An ultralow‐capacitance bidirectional punch‐through transient voltage suppressor
Author(s) -
Zeng Jie,
Jin Hao,
Guo Wei,
Dong Shurong,
Wang Weihuai,
Yu Zhihui
Publication year - 2016
Publication title -
ieej transactions on electrical and electronic engineering
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.254
H-Index - 30
eISSN - 1931-4981
pISSN - 1931-4973
DOI - 10.1002/tee.22293
Subject(s) - capacitance , electrostatic discharge , electrical engineering , voltage , transient (computer programming) , materials science , transient voltage suppressor , transient analysis , robustness (evolution) , transmission line , optoelectronics , leakage (economics) , transient response , electronic engineering , engineering , computer science , physics , chemistry , electrode , biochemistry , quantum mechanics , gene , operating system , macroeconomics , economics
A bidirectional punch‐through transient voltage suppressor based on a five‐layer N ++ P + PP + N ++ structure is developed. By realizing the device using a 12‐finger layout, transmission line pulse measurements indicate that the device has met the IEC61000‐4‐2 standard with electrostatic discharge robustness of ±8 kV and has an ultralow capacitance value of less than 0.17 pF. Under 3.3 V forward or reverse bias, the device exhibits a leakage current of less than 2 nA. These excellent figures suggest that the developed structure is well suited for actual system‐level protection applications. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.
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