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Recent progress on CMOS successive approximation ADCs
Author(s) -
Matsuura Tatsuji
Publication year - 2016
Publication title -
ieej transactions on electrical and electronic engineering
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.254
H-Index - 30
eISSN - 1931-4981
pISSN - 1931-4973
DOI - 10.1002/tee.22290
Subject(s) - oversampling , cmos , electronic engineering , successive approximation adc , converters , computer science , operational amplifier , shaping , amplifier , noise (video) , signal to noise ratio (imaging) , distortion (music) , electrical engineering , engineering , telecommunications , artificial intelligence , voltage , capacitor , image (mathematics)
Recent progress in CMOS integrated successive approximation (SAR) analog‐to‐digital converters (ADCs) is remarkable in terms of architecture and performance. Because of the inherent non‐necessity of active circuit elements such as operational amplifiers, the SAR architecture is suitable for fine CMOS processes. By using a time‐interleaved architecture, it achieves a very high speed conversion rate of 90 G‐sample/s with an 8‐bit resolution. Also, for applications with very low power consumption, such as wireless sensor nodes, it achieves 84 nW at 10‐bit, 200 k‐sample/s. A high signal to noise and distortion ratio (SNDR) can also be achieved by using several techniques such as an SAR architecture that combines oversampling and noise shaping. This survey paper explains the progress made recently in SAR‐ADC circuit techniques and the achieved performances. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.