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A 0.5‐V 5.9‐fJ/conversion‐step SAR ADC in 0.18‐μm CMOS
Author(s) -
Ren Xiaojiao,
Zhuang Yiqi,
Li Xiaoming,
Qi Zengwei,
Wang Bo
Publication year - 2016
Publication title -
ieej transactions on electrical and electronic engineering
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.254
H-Index - 30
eISSN - 1931-4981
pISSN - 1931-4973
DOI - 10.1002/tee.22263
Subject(s) - effective number of bits , successive approximation adc , cmos , capacitor , electronic engineering , figure of merit , voltage , shaping , electrical engineering , power consumption , power (physics) , computer science , engineering , physics , quantum mechanics , computer vision
In this paper, we present a 434‐nW 8‐bit successive approximation register analog‐to‐digital converter (SAR ADC). We mainly consider the optimization of power consumption. A modified split‐capacitor array involving a novel switching scheme is proposed, which reduces the switching power consumption to just 13.8 C V ref 2for the single‐ended scheme without any losses in performance. Based on the SMIC CMOS 0.1 μ m EEPROM 2P4M process, the simulation results show that at 0.5 V supply voltage, 300 kS/s sample frequency, and 4.98 kHz input frequency, the ADC achieves an signal‐to‐noise‐plus‐distortion ratio (SNDR) of 49.58 dB and effective number of bits (ENOB) of 7.94, and consumes 434 nW, resulting in a figure of merit of 5.9 fJ/conversion step. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.