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High‐efficiency CMOS push‐pull power amplifier with multilayer center‐tapped transformer
Author(s) -
Nakamura Shingo,
Kanemoto Daisuke,
Sadakiyo Tomoki,
Kanaya Haruichi
Publication year - 2016
Publication title -
ieej transactions on electrical and electronic engineering
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.254
H-Index - 30
eISSN - 1931-4981
pISSN - 1931-4973
DOI - 10.1002/tee.22228
Subject(s) - electrical engineering , amplifier , transformer , cascode , cmos , electrical impedance , engineering , transistor , rf power amplifier , input impedance , linearity , power added efficiency , center frequency , electronic engineering , voltage , band pass filter
This paper describes the design of a push‐pull power amplifier (PA) with a center‐tapped transformer for transmitter applications on the 5.2‐GHz band using 0.18 μ m CMOS technology. The type of the proposed PA is based on a double‐ended push–pull (DEPP) configuration. DEPP has a simple construction with only transistors and transformers. The PA has reverse‐phased cascode‐connected transistors. The proposed transformer has a multilayer structure and was designed using electromagnetic field simulation. To achieve high power added efficiency (PAE), we assumed the optimized output impedance technique with a tunable impedance antenna. The PA has 13.2 dB linearity gain, 14.9 dBm 1‐dB compression point (P1dB), and 27.4% maximum PAE. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.