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An XOR‐based parameterization for instruction register files
Author(s) -
Fujieda Naoki,
Ichikawa Shuichi
Publication year - 2015
Publication title -
ieej transactions on electrical and electronic engineering
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.254
H-Index - 30
eISSN - 1931-4981
pISSN - 1931-4973
DOI - 10.1002/tee.22123
Subject(s) - computer science , register file , cache , overhead (engineering) , parallel computing , selection (genetic algorithm) , register (sociolinguistics) , processor register , locality , arithmetic , instruction set , programming language , computer hardware , artificial intelligence , mathematics , memory address , linguistics , philosophy , semiconductor memory
The instruction register file (IRF) shortens and obfuscates instruction sequences by compressing multiple instructions into a packed instruction. The IRF could improve its efficiency by parameterization, but the previously proposed parameterization techniques did not extract the similarity of instructions well. In this paper, we propose an XOR‐based parameterization to utilize the limited capacity of the IRF more efficiently. According to our evaluation, with an improved algorithm of instruction selection, our approach makes 20.2% more dynamic instructions IRF‐resident than the previous techniques. It also reduces the number of instruction fetches from the cache by 6.3% on average. We also confirmed that the hardware overhead of our parameterization was about a quarter of the previous one. © 2015 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.