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CMOS high‐precision loser‐take‐all circuit
Author(s) -
Naderi Saatlo Ali,
Ozoguz Serdar
Publication year - 2014
Publication title -
ieej transactions on electrical and electronic engineering
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.254
H-Index - 30
eISSN - 1931-4981
pISSN - 1931-4973
DOI - 10.1002/tee.22028
Subject(s) - cmos , biasing , computer science , voltage , electronic engineering , electronic circuit , range (aeronautics) , current (fluid) , discrete circuit , electrical engineering , current mirror , equivalent circuit , engineering , transistor , aerospace engineering
This paper presents a new current‐mode CMOS loser‐take‐all circuit. The proposed circuit consists of a basic cell that allows implementation of a multi‐input configuration by repeating the cell for each additional input. A high‐speed feedback structure is employed to determine the minimum current among the applied inputs. The significant feature of the circuit is its high accuracy and high‐speed operation. Additionally, the input dynamic range of the circuit can be efficiently controlled via the biasing current. HSPICE simulation results are presented to verify the performance of the circuit, where under a supply voltage of 2.5 V, bias current of 100 µA, and frequency of 10 MHz, the input dynamic range increases within 0–100 µA and the corresponding error remains as low as 0.4%. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.