Realistic model for the multiple‐input floating‐gate transistor | Zendy

CisnerosSinencio Luis Fortino | Zendy; DiazSanchez Alejandro | Zendy; RamirezAngulo Jaime | Zendy; VazquezLeal Hector | Zendy

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Realistic model for the multiple‐input floating‐gate transistor

Author(s) -

CisnerosSinencio Luis Fortino,

DiazSanchez Alejandro,

RamirezAngulo Jaime,

VazquezLeal Hector

Publication year - 2014

Publication title -

ieej transactions on electrical and electronic engineering

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.254

H-Index - 30

eISSN - 1931-4981

pISSN - 1931-4973

DOI - 10.1002/tee.22027

Subject(s) - transistor , cmos , process (computing) , electronic engineering , transistor model , electronic circuit , computer science , circuit design , electrical engineering , voltage , engineering , operating system

Multiple‐input floating‐gate transistor (FGMOS) circuit designers face a serious problem along the design process: the lack of a realistic simulation model. For this reason, a solution that properly predicts the initial voltage at the floating gates is presented in this paper. In order to assess the performance of the proposal, a comparison is made against a test circuit fabricated in a 0.5‐µm On‐Semiconductor CMOS process. Based on this comparison, the proposed model is shown to be a fundamental tool in the design of FGMOS circuits. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

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