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A novel MOSFET with vertical signal‐transfer capability for 3D‐structured CMOS image sensors
Author(s) -
Goto Masahide,
Hagiwara Kei,
Iguchi Yoshinori,
Ohtake Hiroshi,
Saraya Takuya,
Toshiyoshi Hiroshi,
Hiramoto Toshiro
Publication year - 2014
Publication title -
ieej transactions on electrical and electronic engineering
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.254
H-Index - 30
eISSN - 1931-4981
pISSN - 1931-4973
DOI - 10.1002/tee.21974
Subject(s) - mosfet , subthreshold conduction , silicon on insulator , signal (programming language) , cmos , materials science , optoelectronics , image sensor , electrical engineering , electrode , etching (microfabrication) , silicon , subthreshold slope , electronic engineering , transistor , engineering , computer science , nanotechnology , physics , voltage , artificial intelligence , quantum mechanics , layer (electronics) , programming language
We have developed a novel MOSFET that can transfer signals vertically without through‐silicon vias but by using a fully depleted silicon‐on‐insulator ( FDSOI ) structure with its source region connected to the back electrodes as well as the front ones. A prototype MOSFET fabricated using the backside anisotropic wet etching technique has confirmed that the electrical characteristics measured from the front and the back electrodes are identical. The subthreshold factor S of the prototype was found to be 64.5 mV/decade, suggesting a good switching performance. Since the double‐sided MOSFET has vertical signal‐transfer capability and excellent operating characteristics, it is expected to contribute to developing a More‐than‐Moore type device of three‐dimensional integration such as pixel‐parallel image sensors. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.
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