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A nonuniform DPLL architecture for optimized performance
Author(s) -
AlAli Omar AlKharji,
Anani Nader,
AlAraji Saleh,
AlQutayri Mahmoud
Publication year - 2014
Publication title -
ieej transactions on electrical and electronic engineering
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.254
H-Index - 30
eISSN - 1931-4981
pISSN - 1931-4973
DOI - 10.1002/tee.21931
Subject(s) - jitter , phase locked loop , dpll algorithm , computer science , controller (irrigation) , field programmable gate array , lock (firearm) , noise (video) , electronic engineering , block (permutation group theory) , control theory (sociology) , engineering , embedded system , mechanical engineering , agronomy , geometry , mathematics , control (management) , artificial intelligence , image (mathematics) , biology
This paper presents the design, analysis, simulation, and implementation of the architecture of a new nonuniform‐type digital phase‐locked loop (DPLL). The proposed loop uses a composite phase detector (CPD), which consists of a sample‐and‐hold unit and an arctan block. The CPD improves the system linearity and results in a wider lock range. In addition, the loop has an adaptive controller block, which can be used to minimize the overall system sensitivity to variations in the power of the input signal. Furthermore, the controller has a tuning mechanism that gives the designer the flexibility to customize the loop parameters to suit a particular application. These performance parameters include lock range, acquisition time, phase noise or jitter, and signal‐to‐noise ratio enhancement. The simulation results show that the proposed loop provides flexibility to optimize the major conflicting system parameters. A prototype of the proposed system was implemented using a field‐programmable gate array (FPGA), and the practical results concur with those obtained by simulation using MATLAB/Simulink. © 2013 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.