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ESD robustness improvement for integrated DMOS transistors —the different gate‐voltage dependence of I t2 between VDMOS and LDMOS transistors
Author(s) -
Hatasako Kenichi,
Yamamoto Fumitoshi,
Uenishi Akio,
Kuroi Takashi,
Maegawa Shigeto,
Fujiwara Yasufumi
Publication year - 2011
Publication title -
ieej transactions on electrical and electronic engineering
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.254
H-Index - 30
eISSN - 1931-4981
pISSN - 1931-4973
DOI - 10.1002/tee.20669
Subject(s) - ldmos , transistor , materials science , electrostatic discharge , robustness (evolution) , breakdown voltage , optoelectronics , electrical engineering , voltage , engineering , chemistry , biochemistry , gene
This paper presents the device‐level electrostatic discharge (ESD) robustness improvement for integrated vertical double‐diffused MOS (VDMOS) and lateral double‐diffused MOS (LDMOS) transistors by changing device structure. The ESD robustness of VDMOS transistor was improved by preventing current concentration and that of LDMOS transistor was improved by relaxing the electric field under the LOCOS oxide. We found the different gate‐voltage dependence of the second breakdown current ( I t2 ) between VDMOS and LDMOS transistors. © 2011 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.