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SAR ADC Architecture with Digital Error Correction
Author(s) -
Hotta Masao,
Kawakami Masayuki,
Kobayashi Haruo,
San Hao,
Takai Nobukazu,
Matsuura Tatsuji,
Abe Akira,
Yagi Katsuyoshi,
Mori Toshihiko
Publication year - 2010
Publication title -
ieej transactions on electrical and electronic engineering
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.254
H-Index - 30
eISSN - 1931-4981
pISSN - 1931-4973
DOI - 10.1002/tee.20588
Subject(s) - comparator , successive approximation adc , computer science , redundancy (engineering) , cmos , error detection and correction , electronic engineering , reliability (semiconductor) , chip , analog to digital converter , electrical engineering , engineering , voltage , algorithm , power (physics) , telecommunications , operating system , physics , quantum mechanics
This paper describes a high‐performance successive approximation register (SAR) analog to digital converter (ADC) using three comparators operating in parallel, instead of just one as in conventional ADCs. This comparator redundancy enables potentially faster operation, higher reliability, and comparator error correction. Reliability‐enhancement and error‐correction algorithms are described. We designed and implemented a 10‐bit, 6‐Msps SAR ADC with three comparators by using TSMC 0.18 µm CMOS technology. The advantages of high conversion rate and higher accuracy are verified by transistor‐level circuit simulation and experimental results of the test chip. Copyright © 2010 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.