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Variability Analysis of Inverter Delay Time
Author(s) -
Aoki Masakazu,
Hasegawa Ken,
Itayama Keisuke,
Yamawaki Taizo,
Tanaka Satoshi
Publication year - 2010
Publication title -
ieej transactions on electrical and electronic engineering
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.254
H-Index - 30
eISSN - 1931-4981
pISSN - 1931-4973
DOI - 10.1002/tee.20587
Subject(s) - nmos logic , inverter , spice , pmos logic , voltage , transistor , electrical engineering , physics , electronic engineering , materials science , engineering
The variation characteristics of the inverter delay time in a large‐scale integrated (LSI) chip were evaluated by using an analytical model equation combined with the statistical simulation program with integrated circuit emphasis (SPICE) simulation as well as the experimental data obtained from a device matrix array (DMA) test vehicle 11. We demonstrate that the variation in the two‐stage delay time t d ( t d = t dLH + t dHL ) is linearly proportional to the variation of the effective peak operating current of the two‐stage inverter I D (7) expressed as Δ t d /t d = −Δ I D /I D . This remains constant whether or not the current variation was induced by the threshold voltage variation (Δ V th ), the current factor variation (Δ β ), or both, even for unbalanced transistor width ratios between the p‐type metal oxide semiconductor (PMOS) and the n‐type metal oxide semiconductor (NMOS) ( W P /W N = 0.5–5). Thus Δ I D /I D can be regarded as a measure of the inverter delay time variation. The relative variation in the delay time increases dramatically when the supply voltage is decreased, which we attribute to the specific gate voltage dependence of the MOS drain current variation induced by the threshold voltage variation Δ V th . Copyright © 2010 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.