Design of Fourth‐Order Continuous‐Time Bandpass ΔΣAD Modulator for RF Sampling

This paper presents the design of a fourth‐order continuous‐time bandpass ΔΣAD modulator for RF sampling. It employs subsampling, RF DAC, as well as digital techniques to compensate for finite Q and excess loop delay, and its loop filter uses inverter‐type OTAs; these basic techniques have been described in our previous papers. This paper validates a transistor‐level circuit design of a complete fourth‐order modulator that combines all of the above techniques, and its SPICE simulation results are as follows: the center of the signal band is 2.4 GHz, the sampling frequency is 3.2 GHz, the signal bandwidth is 2 MHz, the peak SNDR is 56 dB, the power consumption from a 1.8‐V supply voltage is 50 mW, and it uses TSMC 0.18‐µ m CMOS process. Copyright © 2010 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.