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Development of RIE‐lag Reduction Technique for Si Deep Etching Using Double Protection Layer Method
Author(s) -
Ohara Junji,
Asami Kazushi,
Takeuchi Yukihiro,
Sato Kazuo
Publication year - 2010
Publication title -
ieej transactions on electrical and electronic engineering
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.254
H-Index - 30
eISSN - 1931-4981
pISSN - 1931-4973
DOI - 10.1002/tee.20506
Subject(s) - deep reactive ion etching , reactive ion etching , etching (microfabrication) , trench , materials science , layer (electronics) , lag , reduction (mathematics) , optoelectronics , deposition (geology) , black silicon , nanotechnology , computer science , geology , mathematics , geometry , computer network , paleontology , sediment
In this study, we have developed a new reactive ion etching (RIE)‐lag reduction technique in Si deep etching. The conventional RIE‐lag reduction technique has a dependence of polymeric layer deposition thickness on mask opening width in the deep reactive ion etching (DRIE) process (Bosch process). However, in our experiment, when the RIE‐lag was suppressed, the polymeric layer on the wider trench bottom remained and caused Black Si under typical process condition. Even if the Black Si is suppressed by optimization of process parameters, it appears when the trench becomes deeper. Therefore, the remaining of the polymeric layer is considered to determine the depth range for the RIE‐lag reduction. In order to avoid this limitation, we have developed a new RIE‐lag reduction technique that forms a double protection layer consisting of polymer and SiO 2 on the trench bottom before the etching step in the DRIE process. The SiO 2 layer formed by O 2 plasma irradiation under polymeric layer has higher ability for removal than that of the polymeric layer and it can be removed clearly without Black Si phenomenon. Experimental result shows that this technique can obtain RIE‐lag free region up to an aspect ratio of 13. Within this aspect ratio range, the RIE‐lag free effect is considered to be applicable not only to trench pattern but also to other two‐dimensional mask patterns except hall pattern. Copyright © 2010 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.