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A design of MOSFET‐C impedance simulation circuits based on a GIC
Author(s) -
Sato Takahide,
Takagi Shigetaka,
Fujii Nobuo
Publication year - 2007
Publication title -
ieej transactions on electrical and electronic engineering
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.254
H-Index - 30
eISSN - 1931-4981
pISSN - 1931-4973
DOI - 10.1002/tee.20208
Subject(s) - electronic engineering , inductance , electronic circuit , resistor , mosfet , capacitor , capacitance , engineering , electrical engineering , computer science , transistor , voltage , physics , electrode , quantum mechanics
This paper proposes a systematic design method of MOSFET‐C impedance simulation circuits based on a generalized immittance converter (GIC). The design method can realize inductance simulation circuits, capacitance multipliers and frequency‐dependent negative resistances (FDNRs) only by MOSFETs, capacitors and two operational amplifiers. Although MOSFETs are used instead of passive resistors, the realized impedance simulation circuits have good linearity since the nonlinearity caused by MOSFETs are cancelled out. The proposed design method derives three inductance simulation circuits, five capacitance multipliers and two FDNRs systematically from a GIC. All of them are summarized in this paper. As an example, inductance simulation circuits are designed by using the proposed design method. The inductance simulation circuits are applied to a filter realization and validity of the design method is confirmed by HSPICE simulations. Copyright © 2007 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.