Premium
High‐Resolution Van der Waals Stencil Lithography for 2D Transistors
Author(s) -
Song Wenjing,
Kong Lingan,
Tao Quanyang,
Liu Qing,
Yang Xiangdong,
Li Jia,
Duan Huigao,
Duan Xidong,
Liao Lei,
Liu Yuan
Publication year - 2021
Publication title -
small
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 3.785
H-Index - 236
eISSN - 1613-6829
pISSN - 1613-6810
DOI - 10.1002/smll.202101209
Subject(s) - materials science , lithography , stencil , resist , optoelectronics , semiconductor , transistor , next generation lithography , stencil lithography , van der waals force , wafer , nanotechnology , electron beam lithography , layer (electronics) , computer science , physics , computational science , quantum mechanics , voltage , molecule
2D semiconductors have attracted tremendous attention as an atomically thin channel for transistors with superior immunity to short‐channel effects. However, with atomic thin structure, the delicate 2D lattice is not fully compatible with conventional lithography processes that typically involve high‐energy photon/electron radiation and unavoidable polymer residues, posing a key limitation for high performance 2D transistors. Here, a novel van der Waals (vdW) stencil lithography technique based on dry mask lamination process is developed. By pre‐fabricating polymethyl methacrylate (PMMA) resist with designed patterns, the whole PMMA mask layers could be mechanically released from the sacrifice wafer and physically laminated on top of various 2D semiconductors. The vdW stencil lithography ensures pristine 2D surface without any high‐energy electron/photon radiation, polymer residues, or chemical doping effects in conventional lithography process; and the soft nature of PMMA enables intimate contact between the mask and the 2D materials without physical gap, leading to ultra‐high resolution down to 60 nm. Together, by applying vdW stencil lithography for 2D semiconductors, high performance transistors are demonstrated. Our method not only demonstrates improved 2D transistor performance without lithography induced damages, but also provides a new vdW stencil lithography technique for 2D materials with high resolution.