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Four‐Bits‐Per‐Cell Operation in an HfO 2 ‐Based Resistive Switching Device
Author(s) -
Kim Gun Hwan,
Ju Hyunsu,
Yang Min Kyu,
Lee Dong Kyu,
Choi Ji Woon,
Jang Jae Hyuck,
Lee Sang Gil,
Cha Ik Su,
Park Bo Keun,
Han Jeong Hwan,
Chung TaekMo,
Kim Kyung Min,
Hwang Cheol Seong,
Lee Young Kuk
Publication year - 2017
Publication title -
small
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 3.785
H-Index - 236
eISSN - 1613-6829
pISSN - 1613-6810
DOI - 10.1002/smll.201701781
Subject(s) - nand gate , reliability (semiconductor) , flash (photography) , flash memory , tin , non volatile memory , computer science , state (computer science) , switching time , materials science , optoelectronics , electrical engineering , logic gate , electronic engineering , computer hardware , engineering , algorithm , physics , power (physics) , quantum mechanics , optics , metallurgy
The quadruple‐level cell technology is demonstrated in an Au/Al 2 O 3 /HfO 2 /TiN resistance switching memory device using the industry‐standard incremental step pulse programming (ISPP) and error checking/correction (ECC) methods. With the highly optimistic properties of the tested device, such as self‐compliance and gradual set‐switching behaviors, the device shows 6σ reliability up to 16 states with a state current gap value of 400 nA for the total allowable programmed current range from 2 to 11 µA. It is demonstrated that the conventional ISPP/ECC can be applied to such resistance switching memory, which may greatly contribute to the commercialization of the device, especially competitively with NAND flash. A relatively minor improvement in the material and circuitry may enable even a five‐bits‐per‐cell technology, which can hardly be imagined in NAND flash, whose state‐of‐the‐art multiple‐cell technology is only at three‐level (eight states) to this day.