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High Electron Mobility InAs Nanowire Field‐Effect Transistors
Author(s) -
Dayeh Shadi A.,
Aplin David P. R.,
Zhou Xiaotian,
Yu Paul K. L.,
Yu Edward T.,
Wang Deli
Publication year - 2007
Publication title -
small
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 3.785
H-Index - 236
eISSN - 1613-6829
pISSN - 1613-6810
DOI - 10.1002/smll.200600379
Subject(s) - materials science , nanowire , electron mobility , optoelectronics , field effect transistor , metalorganic vapour phase epitaxy , transistor , chemical vapor deposition , capacitance , semiconductor , substrate (aquarium) , leakage (economics) , nanotechnology , layer (electronics) , epitaxy , electrode , electrical engineering , chemistry , voltage , geology , economics , macroeconomics , engineering , oceanography
Single‐crystal InAs nanowires (NWs) are synthesized using metal–organic chemical vapor deposition (MOCVD) and fabricated into NW field‐effect transistors (NWFETs) on a SiO 2 /n + ‐Si substrate with a global n + ‐Si back‐gate and sputtered SiO x /Au underlap top‐gate. For top‐gate NWFETs, we have developed a model that allows accurate estimation of characteristic NW parameters, including carrier field‐effect mobility and carrier concentration by taking into account series and leakage resistances, interface state capacitance, and top‐gate geometry. Both the back‐gate and the top‐gate NWFETs exhibit room‐temperature field‐effect mobility as high as 6580 cm 2 V −1 s −1 , which is the lower‐bound value without interface‐capacitance correction, and is the highest mobility reported to date in any semiconductor NW.