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Complementary Symmetry Silicon Nanowire Logic: Power‐Efficient Inverters with Gain
Author(s) -
Wang Dunwei,
Sheriff Bonnie A.,
Heath James R.
Publication year - 2006
Publication title -
small
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 3.785
H-Index - 236
eISSN - 1613-6829
pISSN - 1613-6810
DOI - 10.1002/smll.200600249
Subject(s) - nanowire , transistor , power (physics) , field effect transistor , silicon , optoelectronics , materials science , nanotechnology , surface (topology) , field (mathematics) , logic gate , silicon nanowires , electrical engineering , physics , computer science , engineering , voltage , mathematics , quantum mechanics , geometry , pure mathematics
Wired for high performance : The role of relative surface area in Si nanowire (NW) transistor (see image) performance was examined by comparing the performance of microwire (μW) field‐effect transistors (FETs) fabricated side‐by‐side with NW FETs. Both n‐ and p‐type NW FETs were found to be more sensitive to surface states than their μW counterparts; these results are utilized to produce NW n‐FETs with consistent performance.