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Realization of a Silicon Nanowire Vertical Surround‐Gate Field‐Effect Transistor
Author(s) -
Schmidt Volker,
Riel Heike,
Senz Stephan,
Karg Siegfried,
Riess Walter,
Gösele Ulrich
Publication year - 2006
Publication title -
small
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 3.785
H-Index - 236
eISSN - 1613-6829
pISSN - 1613-6810
DOI - 10.1002/smll.200500181
Subject(s) - nanowire , materials science , etching (microfabrication) , substrate (aquarium) , field effect transistor , optoelectronics , epitaxy , transistor , realization (probability) , silicon , isotropic etching , nanotechnology , chemical mechanical planarization , electrical engineering , layer (electronics) , oceanography , statistics , mathematics , engineering , voltage , geology
A generic process for fabricating vertical surround‐gate field‐effect transistors (FETs) from epitaxially grown silicon nanowires is presented. The process is demonstrated using n‐type Si nanowires grown on a p‐type substrate in ultrahigh vacuum using a Au catalyst. The process consists of various deposition and etching steps; no chemical or mechanical polishing is required. Individual as well as arrays of vertical surround‐gate FETs can be fabricated.