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A survey of non‐destructive surface characterization methods used to insure reliable gate oxide fabrication for silicon IC devices
Author(s) -
Diebold Alain C.,
Doris Bruce
Publication year - 1993
Publication title -
surface and interface analysis
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.52
H-Index - 90
eISSN - 1096-9918
pISSN - 0142-2421
DOI - 10.1002/sia.740200207
Subject(s) - wafer , characterization (materials science) , ellipsometry , gate oxide , materials science , fabrication , oxide , surface roughness , gate dielectric , surface finish , total internal reflection , silicon , critical dimension , optoelectronics , nanotechnology , transistor , optics , thin film , composite material , electrical engineering , metallurgy , medicine , alternative medicine , engineering , pathology , voltage , physics
As device dimensions decrease below 500 nm, transistors require a gate oxide thickness of <10 nm. Trace organic and inorganic contamination and surface roughness must be minimized before thermal growth of the SiO 2 gate oxide. Both structural defects and contamination can impact device reliability. A variety of diagnostic methods are presently used to either analyze the effectiveness of water cleaning processes or electrically test gate dielectrics after processing. Owing to device dimension, characterization of surface contamination levels is more readily done using unpatterned ‘monitor’ wafers. We discuss automated, non‐destructive ‘in FAB’ analysis using total reflection x‐ray fluorescence, atomic force microscopy and spectroscopic ellipsometry. Total reflection x‐ray fluorescence is already a well‐established ‘in FAB’ technique, and tomic force microscopy and variable‐angle spectroscopic ellipsometer systems designed for ‘in FAB’ use are commercially available at the time of submission of this article. Other FAB‐compatible optical characterization methods are described and contrasted. Microroughness analysis development activities are also described.