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Structural and nanomechanical properties of porous silicon: Cheap substrate for CMOS process industry
Author(s) -
Belaroussi Yasmina,
Scheen Gilles,
Saadi Abdelhalim A.,
Taibi Abdelkader,
Maafri Djabar,
Nysten Bernard,
Gabouze Noureddine,
Raskin JeanPierre
Publication year - 2020
Publication title -
surface and interface analysis
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.52
H-Index - 90
eISSN - 1096-9918
pISSN - 0142-2421
DOI - 10.1002/sia.6885
Subject(s) - materials science , surface roughness , substrate (aquarium) , porosity , silicon , root mean square , surface finish , porous silicon , composite material , cmos , young's modulus , nanoindentation , scanning electron microscope , modulus , atomic force microscopy , optoelectronics , nanotechnology , electrical engineering , oceanography , engineering , geology
The surface topology of porous silicon (PSi) is a relevant parameter that decides the compatibility of such substrate with CMOS process. Using standard resistivity (1–10 Ω·cm) of Si substrate to fabricate PSi‐S is a low cost solution for the industry. In this paper, through an atomic force microscopy (AFM) analysis, the root mean square (RMS) roughness, the power spectral density and the correlation length were determined for different PSi layers. Furthermore, the measured hardness, Young's modulus, and stress have been made for different thicknesses of PSi: 5, 10, 50, and 200 μm. The obtained results demonstrated that very interesting properties have been achieved with the 50 μm‐thick PSi‐S layer with a maximum porosity around 65%, a surface roughness less than 1 nm and a hardness value of (~1 GPa). The realized results encourage the utilization the PSi‐based substrate into the industry process and thus the development of a Systems‐on‐Chip (SoC).