Analysis of GOI‐MOSFET with high‐ k gate dielectric and metal gate fabricated by Ge condensation technique

In order to improve the complementary metal‐oxide‐semiconductor (CMOS) circuit performance under sub‐100 nm technology nodes with low supply voltages, a metal‐oxide‐semiconductor field‐effect transistor (MOSFET) including a high mobility channel and a silicon‐on‐insulator (SOI) structure is a promising device design. According to The International Technology Roadmap for Semiconductors (ITRS), a 25‐nm MOSFET with a gate oxide equivalent oxide thickness (EOT) of 5–8 nm will be produced by 2010. Several groups have reported thermally stable gate dielectrics such as HfO 2 , ZrO 2 , Hf x Si 1− x O, HfO x N y , ZrO x N y , and Ln 2 O 3 . However, considering the relatively thick interfacial layer (∼0.5 nm SiO x ) and the relatively low dielectric constant (10–20) of these materials, it is very difficult to scale down the EOT below 1 nm. In this paper, we report on the electrical characteristics of sputtered HfO 2 with an EOT of 0.78 nm. We report Ge metal‐insulator‐semiconductor field‐effect transistors (MISFETs) with HfO 2 and W/W 2 N metal gate electrode on germanium‐on‐insulator (GOI) wafer obtained by the new graded Ge condensation method. Excellent device characteristics are achieved with a subthreshold swing of 80 mV/dec and low gate leakage. Copyright © 2006 John Wiley & Sons, Ltd.