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P‐13.11: Highly Efficient Electric‐Thermal Simulation for AMOLED Design
Author(s) -
Tong Zhenxiao,
Li Xiangqi,
Lu Taotao
Publication year - 2021
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/sdtp.15368
Subject(s) - amoled , active matrix , flat panel display , parasitic capacitance , design flow , thermal , capacitance , power (physics) , computer science , thermal resistance , electronic engineering , electrical engineering , materials science , engineering , chemistry , physics , electrode , layer (electronics) , quantum mechanics , meteorology , composite material , thin film transistor
Along with the development of advanced display technology, the specification of display panel gets increasingly demanding, taking more factors into consideration in FPD designs. Because of parasitic resistance and capacitance, marked IR‐Drop effects are detected in high resolution display panel, leading to electrical and optical specification defects therein [1,2]. Power/thermal of the power source line serves as a key index affecting complex FPD designs. In this article, we provide a highly efficient full panel electric‐thermal simulation flow, which facilitates designers to accurately assess the effect of IRDrop and then simulate the power/thermal distribution map of a full panel. Precise simulation of device/wire current and voltage as well as current density also helps to optimize active matrix OLED pixel design.