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P‐6.1: 50UD 120Hz LCD TVs Integrated Gate Driver GOA Circuit using Cu/Four‐Mask a‐Si TFT Process
Author(s) -
Dong Hao,
Cho An-thung,
Wu Wen-Bing,
Tsai Yao-Feng,
Zhang Yong,
Hsu James,
Chen Wade
Publication year - 2021
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/sdtp.15302
Subject(s) - ohmic contact , thin film transistor , contact resistance , materials science , optoelectronics , doping , layer (electronics) , semiconductor , electrical engineering , nanotechnology , engineering
A mechanism of high doped N+ film was used to lower the contact resistance between metal and semiconductor to achieve ohmic contact in 4‐mask process. In this article, the improvement mechanism to reduce contact resistance by using high doped N+ layer will be investigated in conjunction with energy level diagram.