Premium
7‐2: Invited Paper: A 40 nm Gate Length Surrounding Gate Vertical‐Channel FET Using Thermally Stable In‐Al‐Zn‐O Channel for 3D CMOS‐LSI Applications
Author(s) -
Sato Yuta,
Fujiwara Hirokazu,
Saito Nobuyoshi,
Ueda Tomomasa,
Ikeda Keiji
Publication year - 2021
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/sdtp.14610
Subject(s) - cmos , channel (broadcasting) , materials science , optoelectronics , transistor , back end of line , thermal stability , gate oxide , electrical engineering , electronic engineering , engineering , voltage , chemical engineering , dielectric
We have developed a CMOS back‐end‐of‐line (BEOL) process compatible oxide semiconductor channel FET with newly proposed In‐Al‐Zn‐O (IAZO) for 3D CMOS‐LSI applications. Compared with In‐Ga‐Zn‐O for active‐matrix display applications, IAZO channel has higher thermal stability (~420°C) suitable for BEOL transistors where suppression of channel shortening is essential. We have successfully demonstrated a surrounding gate vertical‐channel FET with gate length of 40 nm by IAZO channel.