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P‐1.9: The Effect of Lateral Capacitance on Flat‐Panel Display with Gate Driver Circuits Integrated in Active Area
Author(s) -
Xu Shangjun,
Wang Mingxin,
Wang Zhijun,
Zhou Liufei,
Shu Yang,
Yuan Ling,
Bian Cunjian,
Fei Mi,
Wang Lizhong,
Wang Huaipei,
Liu Deyu
Publication year - 2021
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/sdtp.14513
Subject(s) - capacitance , flat panel display , line (geometry) , signal (programming language) , integrated circuit , flat panel , electrical engineering , negative impedance converter , electronic engineering , engineering , computer science , voltage , physics , voltage source , computer graphics (images) , electrode , quantum mechanics , geometry , mathematics , programming language
A highly integrated display panel, in which gate driving circuit was totally integrated in active area, was designed and lit up. The issue of this panel, caused by lateral capacitance between clock signal line and source line, was studied systemically. The results provide reference for the development of higher integrated and more intelligent panel in the future.