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P‐8: Degradation Model of LTPS TFT Aged off‐State Bias Stress on Flexible Substrate
Author(s) -
Kim Kihwan,
Kim Hyojung,
Song Minjun,
Kim Soonkon,
Cho Hyunguk,
Cho Youngmi,
Kim Yongjo,
Choi Byungdeog
Publication year - 2020
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/sdtp.14131
Subject(s) - thin film transistor , materials science , trapping , optoelectronics , stress (linguistics) , substrate (aquarium) , polycrystalline silicon , transistor , silicon , degradation (telecommunications) , charge (physics) , threshold voltage , leakage (economics) , voltage , electronic engineering , electrical engineering , layer (electronics) , nanotechnology , engineering , physics , macroeconomics , ecology , linguistics , biology , quantum mechanics , philosophy , oceanography , economics , geology
We conducted experimental and quantitative studies on the effects of off‐state bias stress on the p‐type polycrystalline silicon thin film transistors (TFTs) on flexible substrate and presented an off‐stress bias stress model(=aging model) of leakage current using TCAD simulation. To understand and model the underlying mechanism of these results, we developed a spatial defect generation and charge trapping model utilizing mapping technique. We had to implement different forms of aging model in the two regions: 1) charge trapping in poly‐Si / oxide interface, and 2) defect creation in the channel bulk. Our aging model quantitatively demonstrates why the GIDL current is lowered accompanied by changes in threshold voltage and asymmetric characteristics.