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60‐4: Implementation and Optimization of FSRCNN‐s Algorithm Based on SDSoC Platform
Author(s) -
Ji Yanan,
Lai Dalton,
Jin Yufeng,
Chen Yin-Hung,
Jou Ming-Jong,
Zhao Bin,
Zhang Xin
Publication year - 2020
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/sdtp.14016
Subject(s) - computer science , static random access memory , process (computing) , algorithm , optimization algorithm , convolution (computer science) , function (biology) , mode (computer interface) , parallel computing , computer hardware , embedded system , mathematical optimization , operating system , artificial neural network , mathematics , artificial intelligence , evolutionary biology , biology
In this paper, traditional FSRCNN‐s algorithm is implemented in hardware platform. The weights of the algorithm are quantified to improve the processing speed and keep the effect. The SDSoc platform is used as the hardware accelerator, and the improved FSRCNN algorithm is optimized again on this platform.The process of hardware optimization includes adjustment of algorithm structure, optimization of SRAM and DDR efficiency, and optimization of de‐convolution calculation. Experimental results show that the algorithm implemented in SDSoC is several times faster than the CPU mode, and the hardware resources consumed can be accepted, finally realizing the super‐resolution function of 960* 540@60hz to 3840* 2160@60hz.